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• 1. [Article] Instability and temperature-dependence assessment of IGZO TFTs

  Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development ...

  Citation × Citation Citation Abstract Copy Title: Instability and temperature-dependence assessment of IGZO TFTs Author: Hoshino, Ken Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. Title: Instability and temperature-dependence assessment of IGZO TFTs Author: Hoshino, Ken Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. Close

• 2. [Article] Fabrication process assessment and negative bias illumination stress study of IGZO and ZTO TFTs

  Indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) are investigated for thin-film transistor (TFT) applications. Negative bias illumination stress (NBIS) is employed for electrical stability assessment. ...

  Citation × Citation Citation Abstract Copy Title: Fabrication process assessment and negative bias illumination stress study of IGZO and ZTO TFTs Author: Hoshino, Ken Indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) are investigated for thin-film transistor (TFT) applications. Negative bias illumination stress (NBIS) is employed for electrical stability assessment. Unpassivated IGZO and ZTO TFTs suffer from severe NBIS instabilities. Zinc-tin-silicon oxide is found to be an effective passivation layer for IGZO and ZTO TFTs, significantly improving the NBIS stability. NBIS instabilities in unpassivated TFTs are attributed to an NBIS-induced desorption of chemisorbed oxygen from the channel layer top surface, exposing surface oxygen vacancies. A ZTSO layer protects the channel layer top surface from adsorbed gas interactions and also appears to reduce the density of oxygen vacancies. The best device architectures investigated with respect to TFT electrical performance are found to be staggered with aluminum electrodes for unpassivated TFTs and coplanar with ITO electrodes for ZTSO-passivated TFTs. Annealing in wet-O₂ is not found to be effective for improving the performance of IGZO or ZTO TFTs or for reducing the post-deposition annealing temperature. Title: Fabrication process assessment and negative bias illumination stress study of IGZO and ZTO TFTs Author: Hoshino, Ken Indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) are investigated for thin-film transistor (TFT) applications. Negative bias illumination stress (NBIS) is employed for electrical stability assessment. Unpassivated IGZO and ZTO TFTs suffer from severe NBIS instabilities. Zinc-tin-silicon oxide is found to be an effective passivation layer for IGZO and ZTO TFTs, significantly improving the NBIS stability. NBIS instabilities in unpassivated TFTs are attributed to an NBIS-induced desorption of chemisorbed oxygen from the channel layer top surface, exposing surface oxygen vacancies. A ZTSO layer protects the channel layer top surface from adsorbed gas interactions and also appears to reduce the density of oxygen vacancies. The best device architectures investigated with respect to TFT electrical performance are found to be staggered with aluminum electrodes for unpassivated TFTs and coplanar with ITO electrodes for ZTSO-passivated TFTs. Annealing in wet-O₂ is not found to be effective for improving the performance of IGZO or ZTO TFTs or for reducing the post-deposition annealing temperature. Close

• 3. [Article] Deposition and Characterization of Pb(Zr₁₋ₓTiₓ)O₃ Thin Films on IGZO and ZTO Substrates for Microelectromechanical Systems

  Pb(Zr₁₋ₓTiₓ)O₃ (PZT) is a common piezoelectric and ferroelectric thin film material with a wide variety of applications, including ferroelectric random access memories, novel thin film transistors, and ...

  Citation × Citation Citation Abstract Copy Title: Deposition and Characterization of Pb(Zr₁₋ₓTiₓ)O₃ Thin Films on IGZO and ZTO Substrates for Microelectromechanical Systems Author: Maack, Bryan A. Pb(Zr₁₋ₓTiₓ)O₃ (PZT) is a common piezoelectric and ferroelectric thin film material with a wide variety of applications, including ferroelectric random access memories, novel thin film transistors, and microelectromechanical systems (MEMS). The most common substrate for PZT in all of these areas has been platinum-coated silicon. Alternative substrates are desired for development of new device architectures. In-Ga-Zn-O (IGZO) and Zn-Sn-O (ZTO) substrates represent two alternative substrates of interest. This work seeks to systematically synthesize and characterize chemical solution deposited PZT on IGZO/SiO₂/Si and ZTO/SiO₂/Si substrates. PZT precursors were synthesized via inverted mixing order chemistry and deposited on IGZO and ZTO substrates which had varying thermal pre-treatments. Interdigitated electrodes were fabricated to allow measurement of film capacitance and dielectric loss in the absence of a platinum bottom electrode. Dielectric constants were calculated from measured capacitance following existing models. Largely phase pure PZT films were fabricated by varying crystallization temperatures and times from 5 to 10 minutes and 750°C to 850°C. Electrical measurements yielded calculated dielectric constants of 300-1100 with variation dependent on the electrode design. Dielectric loss ranged from 4% to 12%. Hysteresis measurements generated well-saturated hysteresis loops with remanent charges from 0.0178 μC to 0.0386 μC and coercive voltages from 23.6 V to 4.81 V. Title: Deposition and Characterization of Pb(Zr₁₋ₓTiₓ)O₃ Thin Films on IGZO and ZTO Substrates for Microelectromechanical Systems Author: Maack, Bryan A. Pb(Zr₁₋ₓTiₓ)O₃ (PZT) is a common piezoelectric and ferroelectric thin film material with a wide variety of applications, including ferroelectric random access memories, novel thin film transistors, and microelectromechanical systems (MEMS). The most common substrate for PZT in all of these areas has been platinum-coated silicon. Alternative substrates are desired for development of new device architectures. In-Ga-Zn-O (IGZO) and Zn-Sn-O (ZTO) substrates represent two alternative substrates of interest. This work seeks to systematically synthesize and characterize chemical solution deposited PZT on IGZO/SiO₂/Si and ZTO/SiO₂/Si substrates. PZT precursors were synthesized via inverted mixing order chemistry and deposited on IGZO and ZTO substrates which had varying thermal pre-treatments. Interdigitated electrodes were fabricated to allow measurement of film capacitance and dielectric loss in the absence of a platinum bottom electrode. Dielectric constants were calculated from measured capacitance following existing models. Largely phase pure PZT films were fabricated by varying crystallization temperatures and times from 5 to 10 minutes and 750°C to 850°C. Electrical measurements yielded calculated dielectric constants of 300-1100 with variation dependent on the electrode design. Dielectric loss ranged from 4% to 12%. Hysteresis measurements generated well-saturated hysteresis loops with remanent charges from 0.0178 μC to 0.0386 μC and coercive voltages from 23.6 V to 4.81 V. Close