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• 1. [Article] Instability and temperature-dependence assessment of IGZO TFTs

  Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development ...

  Citation × Citation Citation Abstract Copy Title: Instability and temperature-dependence assessment of IGZO TFTs Author: Hoshino, Ken Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. Title: Instability and temperature-dependence assessment of IGZO TFTs Author: Hoshino, Ken Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. Close

• 2. [Article] Thin-film transistors with amorphous oxide channel layers

  In recent years, a new class of high-performance thin-film transistors (TFTs) has emerged comprising amorphous oxide channel materials composed of heavy-metal cations (HMCs) with (n-1)d¹⁰ns⁰ (n ≥ 4, where ...

  Citation × Citation Citation Abstract Copy Title: Thin-film transistors with amorphous oxide channel layers Author: Grover, Manan S. In recent years, a new class of high-performance thin-film transistors (TFTs) has emerged comprising amorphous oxide channel materials composed of heavy-metal cations (HMCs) with (n-1)d¹⁰ns⁰ (n ≥ 4, where 'n' refers to the row of the periodic table) electronic configuration. This thesis is devoted to the fabrication and characterization of TFTs employing two such amorphous oxide channels: zinc indium tin oxide (ZITO) and zinc tin oxide (ZTO). ZITO is demonstrated as a transparent and amorphous quaternary channel material for TFTs. Optical transmission of ZITO channels is ~ 85% in the visible portion of the electromagnetic spectrum (~ 400 to 700 nm). Peak incremental mobilities of 5 – 19 cm²V⁻¹s⁻¹ and turn-on voltages of -4 to -17 V are obtained for TFTs post-deposition annealed at 100 – 300°C, respectively. Current-voltage measurements indicate n-channel, depletion-mode transistor operation with excellent drain current saturation, and a drain current on-to-off ratio greater than 10⁶. Additionally, two routes are explored to successfully fabricate enhancement-mode TFTs employing ZTO as the channel layer. Initially, Ba is added to the ZTO material system to obtain BZTO, a low cost quaternary amorphous material system similar to indium gallium zinc oxide. BZTO TFTs are enhancement-mode devices with positive near-zero turn-on voltages and BZTO channels remain amorphous at anneal temperatures as high as 700 – 800°C. However, the incremental mobilities of these devices are less than 5 cm²V⁻¹s⁻¹. Thus, Ba doping is found to be an unsuitable route for enhancement-mode TFT development. Subsequently, an experimental effort is undertaken to optimize the ZTO process for the 1:1 ZnO:SnO₂ stoichiometry. Primarily, the ambient O₂ partial pressure during channel deposition and the post-deposition annealing temperature are deduced to be the two primary processing parameters most significantly impacting TFT performance. Enhancement-mode TFTs are demonstrated for O₂ partial pressure percentages ≤ 5% of the ambient Ar/O₂ processing pressure and annealing temperatures of 300 – 600°C. The best devices realized exhibit incremental mobilities of 10 – 30 cm²V⁻¹s⁻¹ and turn-on voltages of 0 – 5 V. Title: Thin-film transistors with amorphous oxide channel layers Author: Grover, Manan S. In recent years, a new class of high-performance thin-film transistors (TFTs) has emerged comprising amorphous oxide channel materials composed of heavy-metal cations (HMCs) with (n-1)d¹⁰ns⁰ (n ≥ 4, where 'n' refers to the row of the periodic table) electronic configuration. This thesis is devoted to the fabrication and characterization of TFTs employing two such amorphous oxide channels: zinc indium tin oxide (ZITO) and zinc tin oxide (ZTO). ZITO is demonstrated as a transparent and amorphous quaternary channel material for TFTs. Optical transmission of ZITO channels is ~ 85% in the visible portion of the electromagnetic spectrum (~ 400 to 700 nm). Peak incremental mobilities of 5 – 19 cm²V⁻¹s⁻¹ and turn-on voltages of -4 to -17 V are obtained for TFTs post-deposition annealed at 100 – 300°C, respectively. Current-voltage measurements indicate n-channel, depletion-mode transistor operation with excellent drain current saturation, and a drain current on-to-off ratio greater than 10⁶. Additionally, two routes are explored to successfully fabricate enhancement-mode TFTs employing ZTO as the channel layer. Initially, Ba is added to the ZTO material system to obtain BZTO, a low cost quaternary amorphous material system similar to indium gallium zinc oxide. BZTO TFTs are enhancement-mode devices with positive near-zero turn-on voltages and BZTO channels remain amorphous at anneal temperatures as high as 700 – 800°C. However, the incremental mobilities of these devices are less than 5 cm²V⁻¹s⁻¹. Thus, Ba doping is found to be an unsuitable route for enhancement-mode TFT development. Subsequently, an experimental effort is undertaken to optimize the ZTO process for the 1:1 ZnO:SnO₂ stoichiometry. Primarily, the ambient O₂ partial pressure during channel deposition and the post-deposition annealing temperature are deduced to be the two primary processing parameters most significantly impacting TFT performance. Enhancement-mode TFTs are demonstrated for O₂ partial pressure percentages ≤ 5% of the ambient Ar/O₂ processing pressure and annealing temperatures of 300 – 600°C. The best devices realized exhibit incremental mobilities of 10 – 30 cm²V⁻¹s⁻¹ and turn-on voltages of 0 – 5 V. Close

• 3. [Article] Evaluation of amorphous oxide semiconductors for thin film transistors (TFTs) and resistive random access memory (RRAM) applications

  Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs ...

  Citation × Citation Citation Abstract Copy Title: Evaluation of amorphous oxide semiconductors for thin film transistors (TFTs) and resistive random access memory (RRAM) applications Author: Rajachidambaram, Jaana Saranya Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure. Title: Evaluation of amorphous oxide semiconductors for thin film transistors (TFTs) and resistive random access memory (RRAM) applications Author: Rajachidambaram, Jaana Saranya Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure. Close